1. Field of the Invention
The invention relates in general to the development of an integrated circuit design, and more particularly, to the derivation of gated clock circuitry during integrated circuit design.
2. Description of the Related Art
Clock gating is a technique that reduces power dissipation by selectively stopping clock signals to portions of an integrated circuit during time periods when those portions are temporarily inactive. In clocked circuits, a clock signal ordinarily switches at every clock cycle and drives a relatively large capacitance. As a result, the clock signal can be a major source of dynamic power dissipation. Clock gating can reduce dynamic power dissipation of a circuit by preventing unnecessary transitions of sequential elements (e.g., registers, flip-flops) between logic levels. Specifically, for example, clock gating may disable a clock signal on a sequential element during a clock cycle when that element is to retain its current value. Disabling the clock to parts of a circuit that are not actively switching between logic levels during periods of such inactivity can reduce power dissipation. It may also reduce the total capacitance driven by a clock net. Control circuitry can be used to achieve clock gating. The control circuitry passes a clock signal to a circuit portion during clock cycles when that circuit portion may experience a logic transition and blocks the clock signal to that circuit portion during clock cycles when that circuit portion will not experience a logic transition.
Modern integrated circuit (IC) design has evolved into a specialized field often referred to as electronic design automation in which computers and computer aided design (CAD) techniques are used to automate the IC chip design process. Generally, an IC circuit design process begins with an engineer using a hardware design language (HDL) such as Verilog or VHDL, to describe the input/output signals, functionality and performance characteristics of the circuit. This description is provided to a computer that runs a logic synthesis program that generates or compiles a specification defining the integrated circuit in terms of a particular technology (e.g., very large scale integration). The specification may include a netlist that specifies the interconnection of functional cells in the circuit. The specification serves as a template for the design of a physical embodiment of the circuit in terms of transistors, input pins, output pins, wiring and other features involved in the layout of the chip.
F. Theeuwen and E. Seelen, Power Reduction Through Clock Gating by Symbolic Manipulation, VLSI: Integrated Systems on Silicon, R. Reis and L. Calesen, editors, Chapman and Hall, London, 1997 pp. 389–400, teach that it has been found that certain designs, such as microprocessor like designs, include many sequential elements that usually hold their data through most of the clock cycles. In other words, their stored data values change infrequently and ordinarily remain constant through most clock cycles. Logic synthesis programs have been developed that implement such data-holding capability for a given sequential element by producing a netlist that includes a conditional loop back from a data output of such element to its data input. If such loop back is active, then the value stored by the sequential element will not change. A sequential element with such feedback loop functionality may be viewed as being in a hold mode during a clock cycle when its current value is fed back to it as an input signal. Clock gating techniques have been used to avoid unnecessary power dissipation when a sequential element is to operate in a hold mode by stopping the clock to the element during clock intervals when a value stored by the element is to remain unchanged. Since such gated sequential element does not receive a triggering clock, it retains its currently stored value. Thus, clock gating advantageously reduces power dissipation by obviating the need to clock a sequential element when its feedback loop would have propagated its currently stored value back to its input. However, the taught approach does clock gating after logic synthesis, which could destroy the optimized netlist and timing. The computation based on ROBDD makes it difficult to be applied to larger design.
Several techniques have been proposed for inserting clock-gating circuitry into an IC design in order to reduce power consumption. For example, U.S. Pat. No. 6,434,722, entitled, Method of Changing Logic Circuit Portion into Gated Portion and Recording Medium Storing a Program for Carrying Out the Method, issued to Kawarabayashi, et al., teaches automatic extraction of a gated clock from a circuit design. Kawarabayashi et al. discuss as an example a relatively simple circuit design produced by a synthesis program that includes a combination of a multiplexer, a delay flip-flop (i.e., a sequential element) and a feedback loop. The multiplexer operates by receiving a clock enable signal and a data signal. The flip-flop is connected to the multiplexer and is turned on and off by the clock enable signal. The feedback loop is connected between the delay flip-flop and the multiplexer. Kawarabayashi et al. disclose a circuit synthesis technique to convert the above circuit into a low power circuit by removing the multiplexer and replacing it with gating control logic that clocks (or enables) the flip-flop only during clock cycles when its stored value may change. However, the approach taught by Kawarabayashi et al. is somewhat limited in that it discusses a circuit with a sequential element coupled in a feedback loop with only a single multiplexer in the feedback path.
L. Benini and G. De Micheli, Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol., 15, No. 6, June 1996, describe an automated method to insert gated clocks in finite state machines (FSM). The authors observe that during the operation of an FSM, there are conditions during which the FSM is idle and neither its next state nor its output changes. Hence, clocking an FSM in an idle state wastes power. The authors propose clock gating an FSM so that it does not receive a clock signal during idle conditions. Unfortunately, there are shortcomings with the approach proposed by Benini et al. For instance, FSM based clock gating requires FSM extraction and synthesis which itself is a difficult problem. Also, FSM based clock gating design can incur significant capacity constraints on the design process because of the very large number of states to be considered in a typical IC design.
N. Raghavan, V. Akella and S. Bakshi, “Automatic Insertion of Gated Clocks at Register Transfer Level”, 12th International Conference on VLSI Design, Goa, India, 1999, pp. 48–54, describe a register transfer level (RTL) based clock gating approach for VHDL. The authors disclose an algorithm that parses a RTL description of a circuit and determines idle conditions for an operation, i.e., the conditions under which the operation will not be performed. The algorithm involves looking for specific syntactic constructs that describe conditional behavior. For example, in VHDL, these would include if-then-else and case statements. This step involves parsing the RTL code and storing the conditional behavior information in an intermediate format. Next, the algorithm identifies signals and variables that do not change their value under idle conditions. The algorithm then isolates clocked elements associated with each of these signals and variables. A determination is made whether to insert clock gating for individual isolated clocked elements based upon estimates the net power savings that would be obtained by clock gating and the impact of clock gating on critical paths of the circuit. If a determination is made that clock gating should be inserted for a given clocked element, then syntax driven transformation rules are employed to insert a appropriate gated clock RTL description into the design. One drawback to the approach proposed by Raghavan et al. is that clock gating analysis based upon RTL language constructs is somewhat limited because actual design descriptions may not be ideally suited to such analysis. In other words, the RTL description can be difficult to interpret. Also, enumerating idle conditions based upon language constructs can be a difficult problem tantamount to an elaborate truth table. Furthermore, although the authors describe a specific implementation suitable for VHDL this implementation is not so readily adaptable to other hardware description languages such as Verilog.
P. Schoenmaker and J. Theeuwen, “Clock Gating on RT-Level VHDL”, IEEE ACM International Workshop on Logic Synthesis 1998, describe a technique for grouping sequential elements with similar hold conditions so that they can be clocked by the same gated clock circuitry. The authors explain that the addition of clock gating circuitry incurs additional area overhead and power dissipation, and that clock gating circuitry is best justified if it governs enough sequential elements that share a similar hold condition. The technique involves producing a fully expanded description of a design with nets that are flattened. Values are computed for every net using binary decision diagrams (BDDs). When the BDDs for all nets have been computed, they are grouped in hold domains. Each hold domain is governed by its own gated clock. A possible difficulty with the approach suggested by Schoenmaker et al. is that BDDs are compute intensive and potentially not well suited to large-scale designs.
Q. Wu, M. Pedram and X. Wu, “Clock-Gating and Its Application to Low Power Design of Sequential Circuits”, IEEE Transactions on Circuits and Systems, Vol. 47, No. 3, pp. 415–420, propose using a quaternary variable to model clock behavior in a sequential circuit. The up and down transition condition of each flip-flop is derived from a state table. Then a covering relation is computed to find out the so-called transition propagate and transition generate terms. One shortcoming of this proposed approach is that a derivation of transition condition and covering relation may require sophisticated Boolean manipulation which may limit its usefulness for larger real-world designs. The state table based input also may limit its practical use.
Thus, there has been a need for improvement in the synthesis of clock gating circuits. The present invention meets this need.